Haiqing Nan, Kyung Ki Kim, Wei Wang, Ken Choi, Journal of Information Processing Systems Vol. 7, No. 1, pp. 93-102, Mar. 2011  

https://doi.org/10.3745/JIPS.2011.7.1.093
Keywords: PVT Variation sensors, Yield, Voltage Scaling, Frequency Scaling
Fulltext: PDF

Abstract

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel postsilicon tuning methodology to scale optimum voltage and frequency ¡°dynamically¡±. The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated ¡°automatically¡±. During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS¡¯85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.

Statistics
Cite this article