Digital Library

Vol. 8, No. 1, Mar. 2012  

1. Indoor Link Quality Comparison of IEEE 802.11a Channels in a Multi-radio Mesh Network Testbed
   Asitha U B, aranayake, Vaibhav P, it, Dharma P. Agrawal
   Vol. 8, No. 1, pp. 1-20, Mar. 2012  
   https://doi.org/10.3745/JIPS.2012.8.1.001
   Details
   Keywords: IEEE 802.11a, Indoor Test Bed, Link Quality, Wireless Mesh Networks
   Show / Hide Abstract

   The most important criterion for achieving the maximum performance in a wireless mesh network (WMN) is to limit the interference within the network. For this purpose, especially in a multi-radio network, the best option is to use non-overlapping channels among different radios within the same interference range. Previous works that have considered non-overlapping channels in IEEE 802.11a as the basis for performance optimization, have considered the link quality across all channels to be uniform. In this paper, we present a measurement-based study of link quality across all channels in an IEEE 802.11a-based indoor WMN test bed. Our results show that the generalized assumption of uniform performance across all channels does not hold good in practice for an indoor environment and signal quality depends on the geometry around the me routers.


2. Optimal Software Release Using Time and Cost Benefits via Fuzzy Multi-Criteria and Fault Tolerance
   Praveen Ranjan Srivastava
   Vol. 8, No. 1, pp. 21-54, Mar. 2012  
   https://doi.org/10.3745/JIPS.2012.8.1.021
   Details
   Keywords: Software Testing, Fuzzy Multi-Criteria Approach, Fuzzy Logic, Fuzzy Rules Based, Confidence, Centre of Gravity, Fault Tolerance, Kilo Line of Code (KLOC), Software Development Effort (SDE), Software Test Effort (STE), Decision Makers (DM)
   Show / Hide Abstract

   As we know every software development process is pretty large and consists of different modules. This raises the idea of prioritizing different software modules so that important modules can be tested by preference. In the software testing process, it is not possible to test each and every module regressively, which is due to time and cost constraints. To deal with these constraints, this paper proposes an approach that is based on the fuzzy multi-criteria approach for prioritizing several software modules and calculates optimal time and cost for software testing by using fuzzy logic and the fault tolerance approach.


3. A Dual Modeling Method for a Real-Time Palpation Simulator
   Sang-Youn Kim, Sekil Park, Jinah Park
   Vol. 8, No. 1, pp. 55-66, Mar. 2012  
   https://doi.org/10.3745/JIPS.2012.8.1.055
   Details
   Keywords: Haptic Feedback, Dual Model, Palpation, Real-time Simulation, S-chain Model
   Show / Hide Abstract

   This paper presents a dual modeling method that simulates the graphic and haptic behavior of a volumetric deformable object and conveys the behavior to a human operator. Although conventional modeling methods (a mass-spring model and a finite element method) are suitable for the real-time computation of an object"'"s deformation, it is not easy to compute the haptic behavior of a volumetric deformable object with the conventional modeling method in real-time (within a 1kHz) due to a computational burden. Previously, we proposed a fast volume haptic rendering method based on the S-chain model that can compute the deformation of a volumetric non-rigid object and its haptic feedback in real-time. When the S-chain model represents the object, the haptic feeling is realistic, whereas the graphical results of the deformed shape look linear. In order to improve the graphic and haptic behavior at the same time, we propose a dual modeling framework in which a volumetric haptic model and a surface graphical model coexist. In order to inspect the graphic and haptic behavior of objects represented by the proposed dual model, experiments are conducted with volumetric objects consisting of about 20,000 nodes at a haptic update rate of 1000Hz and a graphic update rate of 30Hz. We also conduct human factor studies to show that the haptic and graphic behavior from our model is realistic. Our experiments verify that our model provides a realistic haptic and graphic feeling to users in real-time.


4. Using a Cellular Automaton to Extract Medical Information from Clinical Reports
   Fatiha Barigou, Baghdad Atmani, Bouziane Beldjilali
   Vol. 8, No. 1, pp. 67-84, Mar. 2012  
   https://doi.org/10.3745/JIPS.2012.8.1.067
   Details
   Keywords: Clinical Reports, Information Extraction, Cellular Automaton, Boolean Inference Engine
   Show / Hide Abstract

   An important amount of clinical data concerning the medical history of a patient is in the form of clinical reports that are written by doctors. They describe patients, their pathologies, their personal and medical histories, findings made during interviews or during procedures, and so forth. They represent a source of precious information that can be used in several applications such as research information to diagnose new patients, epidemiological studies, decision support, statistical analysis, and data mining. But this information is difficult to access, as it is often in unstructured text form. To make access to patient data easy, our research aims to develop a system for extracting information from unstructured text. In a previous work, a rule-based approach is applied to a clinical reports corpus of infectious diseases to extract structured data in the form of named entities and properties. In this paper, we propose the use of a Boolean inference engine, which is based on a cellular automaton, to do extraction. Our motivation to adopt this Boolean modeling approach is twofold: first optimize storage, and second reduce the response time of the entities extraction.


5. Hartley Transform Based Fingerprint Matching
   Sangita Bharkad, Manesh Kokare
   Vol. 8, No. 1, pp. 85-100, Mar. 2012  
   https://doi.org/10.3745/JIPS.2012.8.1.085
   Details
   Keywords: biometrics, feature extraction, Hartley Transform, Discrete Wavelet Transform, Fingerprint Matching
   Show / Hide Abstract

   The Hartley transform based feature extraction method is proposed for fingerprint matching. Hartley transform is applied on a smaller region that has been cropped around the core point. The performance of this proposed method is evaluated based on the standard database of Bologna University and the database of the FVC2002. We used the city block distance to compute the similarity between the test fingerprint and database fingerprint image. The results obtained are compared with the discrete wavelet transform (DWT) based method. The experimental results show that, the proposed method reduces the false acceptance rate (FAR) from 21.48% to 16.74 % based on the database of Bologna University and from 31.29% to 28.69% based on the FVC2002 database.


6. Supporting Java Components in the SID Simulation System
   Hasrul Ma'ruf, Hidayat Febiansyah, Jin Baek Kwon
   Vol. 8, No. 1, pp. 101-118, Mar. 2012  
   https://doi.org/10.3745/JIPS.2011.8.1.101
   Details
   Keywords: Embedded System, Simulation System, SID Simulator
   Show / Hide Abstract

   Embedded products are becoming richer in features. Simulation tools facilitate low-costs and the efficient development of embedded systems. SID is an open source simulation software that includes a library of components for modeling hardware and software components. SID components were originally written using C/C++ and Tcl/Tk. Tcl/Tk has mainly been used for GUI simulation in the SID system. However, Tcl/Tk components are hampered by low performance, and GUI development using Tcl/Tk also has poor flexibility. Therefore, it would be desirable to use a more advanced programming language, such as Java, to provide simulations of cutting-edge products with rich graphics. Here, we describe the development of the Java Bridge Module as a middleware that will enable the use of Java Components in SID. We also extended the low-level SID API to Java. In addition, we have added classes that contain default implementations of the API. These classes are intended to ensure the compatibility and simplicity of SID components in Java.


7. An Improved Fast and Secure Hash Algorithm
   Siddharth Agarwal, Abhinav Rungta, R.Padmavathy, Mayank Shankar, Nipun Rajan
   Vol. 8, No. 1, pp. 119-132, Mar. 2012  
   https://doi.org/10.3745/JIPS.2012.8.1.119
   Details
   Keywords: SHA-256, SFHA-256, Improved SFHA-256
   Show / Hide Abstract

   Recently, a fast and secure hash function SFHA . 256 has been proposed and claimed as more secure and as having a better performance than the SHA . 256. In this paper an improved version of SFHA . 256 is proposed and analyzed using two parameters, namely the avalanche effect and uniform deviation. The experimental results and further analysis ensures the performance of the newly proposed and improved SFHA-256. From the analysis it can be concluded that the newly proposed algorithm is more secure, efficient, and practical.


8. Energy Efficient Architecture Using Hardware Acceleration for Software Defined Radio Components
   Chen Liu, Omar Granados, Rol, o Duarte, Jean Andrian
   Vol. 8, No. 1, pp. 133-144, Mar. 2012  
   https://doi.org/10.3745/JIPS.2012.8.1.133
   Details
   Keywords: Software Communication Architecture, Software Defined Radio, Energy Efficiency, FPGA, Cognitive Radio
   Show / Hide Abstract

   In order to make cognitive radio systems a practical technology to be deployed in real-world scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of performance and energy consumption for mobile platforms. In this paper we present a feasibility study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called for most frequently and it requires intensive floating-point computation. Then, we used the Virtex5 Field- Programmable Gate Array (FPGA) to perform a comparison between compiler floatingpoint support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as a 2X speedup and 50% of the overall energy reduction. We achieved this with an increase of the power consumption by no more than 0.68%. This demonstrates the feasibility of the proposed approach.


9. Performance Study of genus 3 Hyperelliptic Curve Cryptosystem
   Daya Gupta, Asok De, Kakali Chatterjee
   Vol. 8, No. 1, pp. 145-158, Mar. 2012  
   https://doi.org/10.3745/JIPS.2012.8.1.145
   Details
   Keywords: Hyperelliptic Curve Cryptosystem(HECC), Secure Hyperelliptic Curve, Hyperelliptic Curve Deffie-Hellman(HECDH), Hyperelliptic Curve Digital Signature Algorithm (HECDSA)
   Show / Hide Abstract

   Hyperelliptic Curve Cryptosystem (HECC) is well suited for all kinds of embedded processor architectures, where resources such as storage, time, or power are constrained due to short operand sizes. We can construct genus 3 HECC on 54-bit finite fields in order to achieve the same security level as 160-bit ECC or 1024-bit RSA due to the algebraic structure of Hyperelliptic Curve. This paper explores various possible attacks to the discrete logarithm in the Jacobian of a Hyperelliptic Curve (HEC) and addition and doubling of the divisor using explicit formula to speed up the scalar multiplication. Our aim is to develop a cryptosystem that can sign and authenticate documents and encrypt / decrypt messages efficiently for constrained devices in wireless networks. The performance of our proposed cryptosystem is comparable with that of ECC and the security analysis shows that it can resist the major attacks in wireless networks.


10. An Efficient Block Cipher Implementation on Many-Core Graphics Processing Units
    Sangpil Lee, Deokho Kim, Jaeyoung Yi, Won Woo Ro
    Vol. 8, No. 1, pp. 159-174, Mar. 2012  
    https://doi.org/10.3745/JIPS.2012.8.1.159
    Details
    Keywords: General-Purpose Computation on a Graphics Processing Unit, SEED Block Cipher, Parallelism, Multi-Core Processors
    Show / Hide Abstract

    This paper presents a study on a high-performance design for a block cipher algorithm implemented on modern many-core graphics processing units (GPUs). The recent emergence of VLSI technology makes it feasible to fabricate multiple processing cores on a single chip and enables general-purpose computation on a GPU (GPGPU). The GPU strategy offers significant performance improvements for all-purpose computation and can be used to support a broad variety of applications, including cryptography. We have proposed an efficient implementation of the encryption/decryption operations of a block cipher algorithm, SEED, on off-the-shelf NVIDIA many-core graphics processors. In a thorough experiment, we achieved high performance that is capable of supporting a high network speed of up to 9.5 Gbps on an NVIDIA GTX285 system (which has 240 processing cores). Our implementation provides up to 4.75 times higher performance in terms of encoding and decoding throughput as compared to the Intel 8-core system.


11. Attack and Correction: How to Design a Secure and Efficient Mix Network
    Kun Peng
    Vol. 8, No. 1, pp. 175-190, Mar. 2012  
    https://doi.org/10.3745/JIPS.2012.8.1.175
    Details
    Keywords: Mix Network, Correction
    Show / Hide Abstract

    Shuffling is an effective method to build a publicly verifiable mix network to implement verifiable anonymous channels that can be used for important cryptographic applications like electronic voting and electronic cash. One shuffling scheme by Groth is claimed to be secure and efficient. However, its soundness has not been formally proven. An attack against the soundness of this shuffling scheme is presented in this paper. Such an attack compromises the soundness of the mix network based on it. Two new shuffling protocols are designed on the basis of Groth"'"s shuffling and batch verification techniques. The first new protocol is not completely sound, but is formally analyzed in regards to soundness, so it can be applied to build a mix network with formally proven soundness. The second new protocol is completely sound, so is more convenient to apply. Formal analysis in this paper guarantees that both new shuffling protocols can be employed to build mix networks with formally provable soundness. Both protocols prevent the attack against soundness in Groth"'"s scheme. Both new shuffling protocols are very efficient as batch-verification-based efficiency-improving mechanisms have been adopted. The second protocol is even simpler and more elegant than the first one as it is based on a novel batch cryptographic technique.