Implementation of Low Complexity FFT, ADC and DAC Blocks of an OFDM Transmitter Receiver Using Verilog

Alok Joshi, Dewansh Aditya Gupta and Pravriti Jaipuriyar
Volume: 15, No: 3, Page: 670 ~ 681, Year: 2019
10.3745/JIPS.03.0119
Keywords: ADC, DAC, DFT, FFT, OFDM, Verilog
Full Text:

Abstract
Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

Article Statistics
Multiple requests among the same broswer session are counted as one view (or download).
If you mouse over a chart, a box will show the data point's value.


Cite this article
IEEE Style
A. Joshi, D. A. Gupta and P. Jaipuriyar, "Implementation of Low Complexity FFT, ADC and DAC Blocks of an OFDM Transmitter Receiver Using Verilog," Journal of Information Processing Systems, vol. 15, no. 3, pp. 670~681, 2019. DOI: 10.3745/JIPS.03.0119.

ACM Style
Alok Joshi, Dewansh Aditya Gupta, and Pravriti Jaipuriyar. 2019. Implementation of Low Complexity FFT, ADC and DAC Blocks of an OFDM Transmitter Receiver Using Verilog, Journal of Information Processing Systems, 15, 3, (2019), 670~681. DOI: 10.3745/JIPS.03.0119.