Energy Efficient Architecture Using Hardware Acceleration for Software Defined Radio Components

Chen Liu, Omar Granados, Rolando Duarte and Jean Andrian
Volume: 8, No: 1, Page: 133 ~ 144, Year: 2012
10.3745/JIPS.2012.8.1.133
Keywords: Software Communication Architecture, Software Defined Radio, Energy Efficiency, FPGA, Cognitive Radio
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Abstract
In order to make cognitive radio systems a practical technology to be deployed in real-world scenarios, the core Software Defined Radio (SDR) systems must meet the stringent requirements of the target application, especially in terms of performance and energy consumption for mobile platforms. In this paper we present a feasibility study of hardware acceleration as an energy-efficient implementation for SDR. We identified the amplifier function from the Software Communication Architecture (SCA) for hardware acceleration since it is one of the functions called for most frequently and it requires intensive floating-point computation. Then, we used the Virtex5 Field- Programmable Gate Array (FPGA) to perform a comparison between compiler floatingpoint support and the on-chip floating-point support. By enabling the on-chip floating-point unit (FPU), we obtained as high as a 2X speedup and 50% of the overall energy reduction. We achieved this with an increase of the power consumption by no more than 0.68%. This demonstrates the feasibility of the proposed approach.

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Cite this article
IEEE Style
C. Liu, O. Granados and R. D. J. Andrian, "Energy Efficient Architecture Using Hardware Acceleration for Software Defined Radio Components," Journal of Information Processing Systems, vol. 8, no. 1, pp. 133~144, 2012. DOI: 10.3745/JIPS.2012.8.1.133.

ACM Style
Chen Liu, Omar Granados, Rolando Duarte and Jean Andrian. 2012. Energy Efficient Architecture Using Hardware Acceleration for Software Defined Radio Components, Journal of Information Processing Systems, 8, 1, (2012), 133~144. DOI: 10.3745/JIPS.2012.8.1.133.